Microsemi Recruitment scheduled for the post of Associate
Engineer at Hyderabad. Check it below.
Microsemi Career Recruitment 2017
Company Profile:
Microsemi Corporation provides semiconductor and system
solutions for aerospace & defense, communications, data center and
industrial markets.
Microsemi is headquartered in Aliso Viejo, California and
has offices in California (Camarillo, Cupertino, Garden Grove, San Diego, San
Jose, Santa Clara, Santa Rosa); Boulder, Colorado; Atlanta, Georgia; Beverly,
Lawrence, and Lowell, Massachusetts; Allentown and Reading, Pennsylvania;
Austin and Dallas, Texas; Ottawa, Canada; Macau, Shanghai and Shenzhen, China;
Herlev, Denmark; Bruges, Belgium; Ennis, Ireland; Hod HaSharon, Israel; Manila
and Cabuyao, Philippines; Caldicot, United Kingdom; and Hyderabad, India. This
list does not include properties acquired together with PMC-Sierra.
Organization Name: Microsemi
Official Site: www.microsemi.com
Job Category: Associate Engineer
Experience: 6 Months – 2 Years
Shift: 1st Shift (Days)
Work Location: Hyderabad
Position Type: Full Time - Regular
Headquarters: Aliso Viejo, California, United States
Job Description:
- Write verification specifications, verification plans, and documentation
- Develop test bench and automate regression plans
- Be responsible for simulations, verifications, and debugging of logic designs (schematics, RTL)
- Be responsible for developing testbenches , test cases and verification flow components for Soc based FPGA
- Develop tests with software/firmware flow used in SoC FPGA verification
- Development of Behavioral models using Verilog and SystemVerilog
- Develop Coverage driven Verification flows
- Develop and complete block-level verification and contribute on test development for SoC FPGA fullchip level verification
- Bring a self-motivated and enthusiastic approach that will achieve any new requirements and overcome all challenges
- Able to work independently with minimal support and handle complex Block and Subsystem Verification platform
- Able to debug the logic designs for design intent and Interface with cross-functional teams and collaboration in all verification related activities
Eligible Details:
- Candidates should possess B.E/B.Tech/M.E/M.Tech/BS/MS in EE/ECE/CSE
- Minimum of 6 months to 2 years of related work experience.
- Hands-on project experience in RTL Verification
- Strong knowledge on digital fundamentals and understanding of FPGA/ custom chip flow
- Hands on knowledge on Verilog and SystemVerilog
- Hands on knowledge in C, C++ language
- Experience in FPGA programming and related software usage with Firmware handling knowledge is a plus
- Exposure to SVF and STAPL/JAM: Adaptive FPGA Programming is a plus
- Good Knowledge in logic design and analysis
- Experience with UNIX shell scripting or Perl scripting
- Experience in Verilog, SystemVerilog Modeling is recommended
- Exposure to SoC FPGA flow concepts
- Exposure to knowledge on System Verilog Assertions, Functional Coverage and Scoreboard development
- Experience with leading edge simulator tools is recommended
- Good analytical and problem solving skills
- Excellent written and verbal communication in English.
- Willingness to travel on short notices occasionally.
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